// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

module Lcd(
	Nce,
	Noe,
	Nwe,
	Clk10K,
	Clk25M,
	LcdRDMemDatBus,
	SysAddrBus,
	SysDatBus,
	LcdPWM,
	LcdDE,
	LcdVS,
	LcdHS,
	LcdRDMemReq,
	LcdClk,
	LcdRdRamDatOut,
	LcdRdRamClk,
	LcdDatBus,
	LcdRDMemAddrBus
);

input	Nce;
input	Noe;
input	Nwe;
input	Clk10K;
input	Clk25M;
input	[15:0] LcdRDMemDatBus;
input	[2:0] SysAddrBus;
input	[15:0] SysDatBus;
output	LcdPWM;
output	LcdDE;
output	LcdVS;
output	LcdHS;
output	LcdRDMemReq;
output	LcdClk;
output	LcdRdRamDatOut;
output	LcdRdRamClk;
output	[15:0] LcdDatBus;
output	[21:0] LcdRDMemAddrBus;

wire	SYNTHESIZED_WIRE_0;
wire	[2:0] SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_14;
wire	SYNTHESIZED_WIRE_15;
wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_16;
wire	[21:0] SYNTHESIZED_WIRE_8;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;

assign	LcdClk = Clk25M;
assign	LcdDatBus = LcdRDMemDatBus;
assign	LcdDE = SYNTHESIZED_WIRE_16;
assign	LcdVS = SYNTHESIZED_WIRE_6;
assign	LcdRdRamDatOut = SYNTHESIZED_WIRE_16;
assign	LcdRdRamClk = SYNTHESIZED_WIRE_16;




LcdPwr	b2v_inst(.Clk10K(Clk10K),
.LcdPwrCtr(SYNTHESIZED_WIRE_0),.LcdBkpConst(SYNTHESIZED_WIRE_1),.LcdPWM(LcdPWM));

LcdReg	b2v_inst1(.Nce(Nce),
.Noe(Noe),.Nwe(Nwe),.SysAddrBus(SysAddrBus),.SysDatBus(SysDatBus),.LcdPwrCtr(SYNTHESIZED_WIRE_0),.LcdCtr(SYNTHESIZED_WIRE_15),.CgramAddr(SYNTHESIZED_WIRE_8),.LcdBkpConst(SYNTHESIZED_WIRE_1));
assign	LcdHS = SYNTHESIZED_WIRE_15 ? SYNTHESIZED_WIRE_14 : 1'bz;

assign	SYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_15 ? SYNTHESIZED_WIRE_4 : 1'bz;


LcdDat	b2v_inst2(.LcdVS(SYNTHESIZED_WIRE_6),
.LcdDE(SYNTHESIZED_WIRE_16),.LcdCgramAddr(SYNTHESIZED_WIRE_8),.LcdRDMemReq(LcdRDMemReq),.LcdRDMemAddrBus(LcdRDMemAddrBus));

LcdHS	b2v_inst4(.Clk25M(Clk25M),
.LcdHS(SYNTHESIZED_WIRE_14),.LcdDE(SYNTHESIZED_WIRE_11));

LcdVS	b2v_inst7(.ClkIn(SYNTHESIZED_WIRE_14),
.LcdVS(SYNTHESIZED_WIRE_4),.LcdDE(SYNTHESIZED_WIRE_10));
assign	SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_10 & SYNTHESIZED_WIRE_11;


endmodule
